The arrayed waveguide grating structure can be used as an important component in high-speed CMOS optical interconnects in silicon-on-insulator (SOI) platform. However, the performance of such device is found to be extremely sensitive to the fabrication-related errors in defining the critical features. In the absence of an appropriate analytical model, one needs to rely on numerical computation to analyze the device characteristics and fabrication tolerances. Because compact design of such a device structure has foot-print and the smallest features can be as small as (waveguide cross section), it demands a huge computational budget to optimize the design parameters. A semi-analytical model using Gaussian beam approximation of guided mode profiles has been developed to analyze the output spectrum of arrayed waveguide grating and to estimate the phase errors due to waveguide inhomogeneities. This model has been validated with existing numerical methods and published experimental results. It has been observed that a probabilistic waveguide width variations of can cause a cross-talk degradation of about 40 dB (25 dB) for a device (operating at ) fabricated on SOI substrate with 220 nm (2 μm) device layer thickness.
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