Abstract

We report a low temperature $({\sim}100^{\circ}{\hbox{C}})$ lithographic method for fabricating hybrid metal oxide/organic field-effect transistors (FETs) that combine a zinc–indium–oxide (ZIO) semiconductor channel and organic, parylene, dielectric layer. The transistors show a field-effect mobility of $({\hbox{12}}\pm {\hbox{0.8}})$ cm$^{2}$V$^{-1}$s$^{-1}$, on/off ratio of 10$^{8}$ and turn-off voltage of $V_{\rm off}= -1$ V. This work demonstrates that organic and inorganic layers can be deposited and patterned using a low temperature budget, integrated lithographic process to make FETs suitable for large area electronic applications.

© 2009 IEEE

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