A potential erroneous and misleading result which is caused by the wrong calculation of current density and transconductance was found in a paper, namely [Opt. Express 22, A1589 (2014)]. After checking the calculation, this paper points out the contradictory results existing in the MOSFET gate width as regards its actual layout and inconsistent I-V characteristics. Judging from the calculation result, we estimate that the author may confuse gate length with gate width in the calculation. Considering the author was conducting an interdisciplinary research and demonstrating a novel device design, these calculation errors may be trivial and comprehensible. But we still suggest that the author can make their work more accurate and comparable with other monolithic integration works by correcting the existing calculation errors.
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