Abstract

A potential erroneous and misleading result which is caused by the wrong calculation of current density and transconductance was found in a paper, namely [Opt. Express 22, A1589 (2014)]. After checking the calculation, this paper points out the contradictory results existing in the MOSFET gate width as regards its actual layout and inconsistent I-V characteristics. Judging from the calculation result, we estimate that the author may confuse gate length with gate width in the calculation. Considering the author was conducting an interdisciplinary research and demonstrating a novel device design, these calculation errors may be trivial and comprehensible. But we still suggest that the author can make their work more accurate and comparable with other monolithic integration works by correcting the existing calculation errors.

© 2017 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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References

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  1. University of California, Berkeley, “MOSFET technology scaling, leakage current, and other topics”, http://inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf .
  2. Y. J. Lee, Z. P. Yang, P. G. Chen, Y. A. Hsieh, Y. C. Yao, M. H. Liao, M. H. Lee, M. T. Wang, and J. M. Hwang, “Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors,” Opt. Express 22(106Suppl 6), A1589–A1595 (2014).
    [PubMed]
  3. C. M. Lee and B. Y. Tsui, “High-performance poly-Si nanowire thin-film transistors using the HfO2 gate dielectric,” IEEE Electron Device Lett. 32(3), 327–329 (2011).

2014 (1)

2011 (1)

C. M. Lee and B. Y. Tsui, “High-performance poly-Si nanowire thin-film transistors using the HfO2 gate dielectric,” IEEE Electron Device Lett. 32(3), 327–329 (2011).

Chen, P. G.

Hsieh, Y. A.

Hwang, J. M.

Lee, C. M.

C. M. Lee and B. Y. Tsui, “High-performance poly-Si nanowire thin-film transistors using the HfO2 gate dielectric,” IEEE Electron Device Lett. 32(3), 327–329 (2011).

Lee, M. H.

Lee, Y. J.

Liao, M. H.

Tsui, B. Y.

C. M. Lee and B. Y. Tsui, “High-performance poly-Si nanowire thin-film transistors using the HfO2 gate dielectric,” IEEE Electron Device Lett. 32(3), 327–329 (2011).

Wang, M. T.

Yang, Z. P.

Yao, Y. C.

IEEE Electron Device Lett. (1)

C. M. Lee and B. Y. Tsui, “High-performance poly-Si nanowire thin-film transistors using the HfO2 gate dielectric,” IEEE Electron Device Lett. 32(3), 327–329 (2011).

Opt. Express (1)

Other (1)

University of California, Berkeley, “MOSFET technology scaling, leakage current, and other topics”, http://inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf .

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Figures (1)

Fig. 1
Fig. 1 Schematic to illustrate MOSFET gate length and gate width definition.

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